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| not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs t7570 programmable pcm codec with hybrid-balance filter document id# 080999 date: nov 01, 2002 rev: a version: 1 distribution: public features programmable internal hybrid-balance network programmable transmit gain ? 19.4 db range, 0.1 db step size programmable receive gain ? 19.4 db range, 0.1 db step size dual-programmable pcm interface ? up to 64 time slots per frame ? variable data rate (64 khz to 4.096 mhz) ? two timing modes programmable -law or a-law companding 300 ? drive receive amplifier analog and digital loopbacks on-chip sample-and-hold, autozero, and precision volt- age reference single 5 v power supply latch-up free, low-power cmos technology ? 70 mw typical operating power dissipation ? 1.5 mw typical standby power dissipation serial microprocesso r-control interface 6-pin parallel i/o latch ttl- and cmos-compatible digital i/o meets or exceeds d3/d4 (as per legerity pub 43801), itu-t (formerly ccitt) g.711?g.712, and lssgr requirements operating temperature range: ?40 c to +85 c description the legerity?s t7570 programmable pcm codec with hybrid-balance filter is a pr ogrammable pcm codec with an internal hybrid-balance netw ork filter. it provides ana- log-to-digital and digital-to-analog conversion, as well as the transmit and receive filter ing necessary to interface a voice telephone circuit to a time-division multiplexed (tdm) system. programmable features include transmit gain setting over a 19.4 db range and receive gain setting over a 19.4 db range. an in ternal filter can be pro- grammed to provide hybrid balancing over a wide range of loop impedances for both active and transformer sub- scriber line interface circuits (slic). the device is programmed over a low pin-count, standard, serial, microprocessor-control interface. a 6-pin parallel input/output latch is provided to contro l interface circuits. each of these pins can be individually programmed to be an input or an output. the t7570 is fabricated by using a low-power cmos technology, requires a single 5 v supply, and is available in a 28-pin plcc package for surface mounting.
not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 2 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 table of contents content page features ...................................................................................................................... ...................................................................1 description ................................................................................................................... ................................................................1 pin information ............................................................................................................... ..............................................................3 functional description ........................................................................................................ .........................................................5 powerup initialization ........................................................................................................ ......................................................5 powerdown state ............................................................................................................... .......................................................5 transmit filter and encoder ................................................................................................... ..................................................5 decoder and receive filter ........ .............. .............. .............. .............. .............. ............ .......... ..................................................6 pcm interface ........... .............. .............. .............. .............. .............. ............ ........... ......... .........................................................6 serial control port ........................................................................................................... .........................................................6 programmable functions ........................................................................................................ .................................................7 hybrid-balance filter ................. ........................................................................................ ....................................................11 programming the filter ........................................................................................................ ..................................................12 absolute maximum ratings ...................................................................................................... .................................................13 handling precautions .......................................................................................................... ........................................................13 electrical characteris tics .................................................................................................... ........................................................14 dc characteristics ............................................................................................................ .......................................................14 transmission characteristics .................................................................................................. ....................................................15 timing characteristics ........................................................................................................ ........................................................20 applications .................................................................................................................. ..............................................................25 outline diagrams .............................................................................................................. ..........................................................26 28-pin plcc ................................................................................................................... .......................................................26 ordering information .......................................................................................................... ........................................................27 not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 3 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter description (continued) figure 1. block diagram pin information figure 2. pin diagram 5-2786 (c) interface latches il5 il4 il3 il2 il1 il0 control register ci co cclk cs mr mclk d r 1 d r 0 bclk fs r fs x tsx1 tsx0 d x 1 d x 0 rx register tx register az timeslot assigment decoder vf r o vf x i receive filter balance filter hybrid v ref transmit filter encoder digital loopback analog loopback 5-2787 (f) il1 il4 il5 fs x ts x 1 ts x 0 il3 fs r d r 1 d r 0 5 6 7 8 9 10 11 4212827 3 12 14 15 16 17 18 13 25 24 23 22 21 20 19 gnd mr ci d x 0 mclk cs cclk bclk il2 nc co d x 1 v dd vf x i vf r o nc nc 26 il0 t7570 - - - ml2 not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 4 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 pin information (continued) table 1. pin description pin symbol type name/description 1gnd? ground . all analog and digital signals are referenced to this pin. 2vf r oo receive analog power amplifier output. this pin can drive load impedances as low as 300 ? . pcm data received on the assigned d r pin is decoded and appears at this output as a voice- frequency signal. 3nc? no connect. connections may be made to or tr aces may be routed through this pin. 4 5 nc ? no connects. do not make connections to or route traces through pins 4 and 5. 6 7 il3 il2 i/o i/o interface latch i/o. these pins can be individually programmed as inputs or outputs as deter- mined by the state of the corresponding bits in the latch direction register (ldr). for pins con- figured as inputs, the logic state sensed on each input is latched into th e interface latch register (ilr) whenever control data is written to the t7570, and the information is shifted out on the co pin. when configured as outputs, control data written into the ilr appears at the corre- sponding il pins. 8fs r i receive frame-sync input. a pulse or square-wave waveform with an 8 khz repetition rate is applied to this inpu t to define the start of the receive tim e slot assigned to this device (nonde- layed frame mode), or the start of the receive frame (delayed frame mode using the internal time-slot assignment counter). 9 10 d r 1 d r 0 i i receive pcm inputs. these receive data input(s) are inactive except during the assigned receive time slot of the assigned port when th e receive pcm data is shifted in on the falling edges of bclk. 11 co o control output. serial control information is shifted out from the t7570 on this pin when cs is low. it can be connected to ci if required. 12 ci i control input. serial control information is shifted into the t7570 on this pin when cs is low. it can be connected to co if required. 13 cclk i control clock. this clock shifts serial control information into ci or out from co when the cs is low, depending on the current instruction. cclk can be asynchronous with the other system clocks. 14 cs i chip select (active-low). when this pin is low, control information can be written into or read from the t7570 vi a the ci and co pins. 15 mr i master reset. this logic input must be pulled low for normal operation of the t7570. when pulled momentarily high (at least 1 s), all programmable registers in the device are reset to the states specified under powerup initialization. 16 bclk i bit clock input. this pin shifts pcm data into and out of the d r and d x pins. bclk can vary from 64 khz to 4.096 mhz in 8 khz increments and must be synchronous with mclk at the start of each frame. mclk can be used as bclk. 17 mclk i master clock. the master-clock input is used by the switched capacitor filters and the encoder and decoder sequencing logic. it must be 1.536 mhz, 1.544 mhz, 2.048 mhz, or 4.096 mhz and must be sync hronous with bclk at the start of each frame. 18 19 d x 0 d x 1 o o transmit pcm output. these transmit-data, high-impedance state outputs remain in the high- impedance state except during the assigned transmit time slot on the assigned port, during which the transmit pcm data byte is shifted out on the rising edges of bclk. 20 21 ts x 0 ts x 1 o o backplane line driver enable (active-low). normally, these open-drai n outputs are floating in a high-impedance state. when a ti me slot is active on one of the d x outputs, the appropriate ts x output pulls low to enab le a backplane line driver. not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 5 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter pin information (continued) table 1. pin description (continued) pin symbol type name/description 22 fs x i transmit frame-sync input. a pulse or square-wave waveform with an 8 khz repetition rate is applied to this input to define the start of the transmit time slot assigned to this device (nonde layed frame mode) or the start of the transmit frame (delayed frame mode us ing the internal time-slot assignment counter). if only the receive channel is being used, it is still necessary to apply the transmit frame-sync every frame. 23 24 25 26 il5 il4 il1 il0 i/o i/o i/o i/o interface latch. see pin 6. 27 v dd ? 5 v 5% power supply. 28 vf x ii transmit analog high-impedance input. voice-frequency signals present on this input are encoded as an a-law or -law pcm bit stream and are shifted out on the selected d x pin. functional description powerup initialization when power is first applied, powerup reset circuitry initial- izes the t7570 and puts it in to the powerdown state. the gain control registers for the transmit and receive gain sec- tions are programmed to off, the hybrid- balance circuit is turned off, the power amp is disabled, and the device is in the nondelayed timing mode. the latch direc- tion register (ldr) is preset w ith all il pins programmed as inputs, placing the interface pins in a high-impedance state. the ci is ready for the first co ntrol byte of the initialization sequence. other initial states in the control register are indi- cated in the control register instruction section under pro- grammable functions. a reset to these same initial co nditions can also be forced by driving the mr pin momentarily high for at least 1 s. this can be done either on powerup or powerdown. for normal operation, this pin must be pulled low. the desired modes for all programmable functions can be initialized via the serial cont rol port prior to a powerup com- mand. powerdown state following a period of activity in the powerup state, the pow- erdown state can be entered by writing any of the control instructions into the serial control port with the p bit set to 1, as indicated in table 2. the powerdown instruction can be included within any other instruction code. it is recommen ded that the chip be powered down before executing any instructions. in the powerdown state, all nonessential circuitr y is de-activated and the d x 0 and d x 1 outputs are in the high-impedance condition. the coefficients stored in th e hybrid-balance circuit and the gain control registers, the data in the ldr and ilr, and all control bits remain unchanged in the powerdown state unless changed by writing new data via the serial control port, which remains active. the outputs of the interface latches also remain active, maintaining the ability to monitor and control interface circuits like a slic. transmit filter and encoder the transmit section input, vf x i, provides a high-impedance load to the line-interface circui t. the input signal is summed with the internal hybrid cancellation signal. the resulting signal is the input to a programmable gain or attenuation amplifier that is controlled by the contents of the transmit gain register (see programmabl e functions section). the sig- nal is then passed through an antialiasing filter followed by a fifth-order, low-pass and thir d-order, high-pass, switched- capacitor filter. after the filter, the a/d converter translates the signal into pcm data for transmission. the a/d not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 6 legerity, inc. t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 functional description (continued) transmit filter and encoder (continued) converter has a compressing ch aracteristic according to the standard itu-t a- or -coding laws selected by a control instruction (see tables 2 and 3). a precision on-chip voltage reference helps ensure accurate and highly stable transmis- sion levels. any offset voltage arising in the gain-set ampli- fier, the filters, or the comparator is can celed by an internal autozero circuit. decoder and receive filter pcm data is shifted into the decoder's receive pcm register via the d r 0 or d r 1 pin during the selected time slot on eight falling edges of bclk. the decoder consists of an expand- ing digital-to-analog convertor with either a- or -law decoding characteristic, which is selected by the same con- trol instruction used to select the encode law. following the decoder is a fifth-order, low- pass, switched-capacitor filter with sin(x)/x correction for the 8 khz sample and hold. a programmable gain amplifier that is set by writing to the receive gain register is include d, followed by a power ampli- fier capable of driving a 300 ? load to 4.0 v peak to peak. pcm interface the fs x and fs r frame-sync inputs determine the beginning of the 8-bit transmit and receive time slots, respectively. they can have any duration from a single cycle of bclk high to one mclk period low. two different relationships can be established between the frame-sync inputs and the actual time slots on the pcm buses by setting bit 3 in the control register (see table 3). nondelayed data mode is similar to long-frame timing of other codecs for which time slots begin nominally coincident with the rising edge of the appropri ate fs input. the alternative is to use delayed-data mode in which each fs input must be high at least a half-cycle of bclk earlier than the time slot. the time-slot assignment circuit on the device can only be used with delayed-data timing. the time-slot assignment capability of this device is a subset of the legerity co ncentration highway interface. the begin- ning of the first time slot in a frame is identified by the appropriate fs input. the actua l transmit and receive time slots are then determined by th e internal time-slot assign- ment counters. transmit and receive frames and time slots can be skewed from each other by an y number of bclk cycles by offset- ting fs r and fs x . during each assigned transmit time slot, the selected d x 0/1 output shifts data out from the pcm reg- ister on the rising edges of bclk. ts x 0 (or ts x 1 as appro- priate) also pulls low for the first 7.5 bit times of the time slot to control the high-imped ance state enable of a back- plane line driver. serial pcm data is shifted into the selected d r 0/1 input during each assigned receive time slot on the falling edges of bclk. d x 0 or d x 1 and d r 0 or d r 1 are selectable on the t7570 (see the port selection section under programmable functions). serial control port programmable register instructions (table 2) are written into or read back from the t7570 via the serial control port con- sisting of the control clock (ccl k), the serial data input (ci) and output (co), and the chip-select input (cs ) (see figure 6). all instructions require 2 bytes, with the exception of a single-byte powerup/powerdown command. the bits in byte 1 are defined as follows: bit 7 specifies powerup or power- down; bits 6, 5, 4, and 3 specify the register address; bit 2 specifies whether the instructio n is a read or a write; bit 1 specifies a one-byte or two-byte instruction; and bit 0 is not used. prior to the initial register write, after powerup or master reset, cclk must be cycled a minimum of one time. to shift control data into the t7570, cclk must be pulsed high eight times while cs is low. data on the ci input is shifted into the serial input register on the falling edge of each cclk pulse. after all data is shifted in, the contents of the input shift register are d ecoded and can indicate that a second byte of control data follows. this second byte can either be defined by a second byte wide cs pulse or can fol- low the first contiguously; it is not mandatory for cs to return high between the first and second control bytes. at the end of the ei ghth cclk pulse in the second control byte, the data is loaded into the appropriate programmable register. cs can remain low continuously when program- ming successive registers, if desired. however, cs should be set high when no data transfers are in progress. to read back interface latch data or status in formation from the t7570, the first byte of th e appropriate instruction, as defined in table 2, is strobed in during the first cs pulse. cs must then be taken low for a further eight cclk cycles, dur- ing which the data is shifted onto the co pin on the rising edges of cclk. when cs is high, the co pin is in the high- impedance state, enabling the co pins of many devices to be multiplexed together. not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 7 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter functional description (continued) programmable functions any of the programmable regist ers can be modified while the device is powered up or down. powerup/powerdown control following powerup initialization, powerup and powerdown control can be accomplished by writing any of the control instructions listed in table 2 into the t7570, with the p bit set to 0 for powerup or 1 for powerdown. normally, it is recom- mended that all programmable functions be initially pro- grammed while the device is powered down. power-state control can then be included with the last programming instruction or in a separate single-byte instruction. when the powerup or powerdown control is entered as a single-byte instruction, bit 1 must be 0. when a powerup command is given, all deactivated circuits are activated, but the pcm outputs, d x 0 and d x 1, remain in the high-impedance stat e until the second fs x pulse after powerup. control register instruction the first byte of a read or writ e instruction to the control reg- ister is as shown in table 2. the second byte has the bit functions shown in tables 3, 5, 6, 7, 8, and 9. table 2. programmable register instructions notes: bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the ci and co pins. x = don't care. p is the powerup/down control bit (0 = powerup, 1 = powerdown); see powerup/powerdown control section. other register address codes are invalid and should not be used. function byte 1 byte 2 pdn address r/w p2 x data 76543210 single-byte powerup/powerdown p x x x x x 0 x none write control register p 0 0 0 0 0 1 x see table 3. read control register p 0 0 0 0 1 1 x write interface latch register p 0 0 0 1 0 1 x see table 6. read interface latch register p 0 0 0 1 1 1 x write latch direction register p 0 0 1 0 0 1 x see table 5. read latch direction register p 0 0 1 0 1 1 x write receive gain register p 0 1 0 0 0 1 x see table 9. read receive gain register p 0 1 0 0 1 1 x write transmit gain register p 0 1 0 1 0 1 x see table 8. read transmit gain register p 0 1 0 1 1 1 x write hybrid-balance register 1 p 0 1 1 0 0 1 x these bits are defined by the legerity t7570 hybrid- balance software program. contact your legerity account represen- tative for a copy of this software. read hybrid-balance register 1 p 0 1 1 0 1 1 x write hybrid-balance register 2 p 0 1 1 1 0 1 x read hybrid-balance register 2 p 0 1 1 1 1 1 x write hybrid-balance register 3 p 1 0 0 0 0 1 x read hybrid-balance register 3 p 1 0 0 0 1 1 x write receive time slot/port p 1 0 0 1 0 1 x see table 7. read receive time slot/port p 1 0 0 1 1 1 x (receive instruction) write transmit time slot/port p 1 0 1 0 0 1 x see table 7. read transmit time slot/port p 1 0 1 0 1 1 x (transmit instruction) not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 8 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 functional description (continued) programmable functions (continued) control register instruction (continued) table 3. control register byte 2 functions * state at powerup initialization (bit 4 = 0). table 4. coding law conventions note: the msb is always the first pcm bit shifted in or out of the t7570. bit number and name function 76543210 f 1 f 0 ma ia dn dl al pp 0 0 ??????reserved 0 1 ? ? ? ? ? ? mclk = 1.536 mhz or 1.544 mhz 1 0 ??????mclk = 2.048 mhz* 1 1 ??????mclk = 4.096 mhz ?? 0 x ???? -law* ? ? 1 0 ? ? ? ? a-law, including even bit inversion ?? 1 1 ????a-law, no even bit inversion ? ? ? ? 0 ? ? ? delayed data timing ? ? ? ? 1 ? ? ? nondelayed data timing* ? ? ? ? ? 0 0 ? normal operation* ? ? ? ? ? 1 x ? digital loopback ? ? ? ? ? 0 1 ? analog loopback ? ? ? ? ? ? ? 0 power amp enabled in powerdown ? ? ? ? ? ? ? 1 power amp disabled in powerdown* v in -law msb lsb true a-law with even bit inversion msb lsb a-law without even bit inversion msb lsb v in = + full scale v in = 0 v v in = ? full scale 10000000 11111111 00000000 10101010 11010101 00101010 111111111 10000000 01111111 master clock frequency selection a master clock must be provided to the t7570 for operation of the filter and coding/decoding functions. the mclk fre- quency must be either 1.536 mhz, 1.544 mhz, 2.048 mhz, or 4.096 mhz and must be syn- chronous with bclk at the st art of each frame. bits f 0 and f 1 (see table 3) must be set duri ng initialization to select the correct internal divider. coding law selection bits ma and ia in table 3 permit the selection of -law cod- ing or a-law coding, with or without even bit inversion. analog loopback the analog loopback mode is entered by setting the al and dl bits in the control register as shown in table 3. in the analog loopback mode, the transmit input vf x i is isolated from the input pin and internally connected to the vf r o out- put, forming a loop fr om the receive pcm register back to the transmit pcm register. the vf r o pin remains active, and the programmed settings of the transmit and receive gains remain unchanged; theref ore, care must be taken to ensure that overload levels ar e not exceeded anywhere in the loop. it is recommended that th e hybrid-balance filter be dis- abled during analog loopback. not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 9 legerity, inc. data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter functional description (continued) programmable functions (continued) digital loopback the digital loopback mode is entered by setting the al and dl bits in the control register as shown in table 3. this mode provides another stage of path verification by enabling data written into the receive pc m register to be read back from that register in any transmit time slot at d x 0/1. in digi- tal loopback mode, the decoder remains functional and out- puts a signal at vf r o. if this is undesirable, the receive output can be disabl ed by programming the receive gain reg- ister to all 0s. interface latch directions immediately following powerup, all interface latches assume they are inputs and, therefore, all il pins are in a high- impedance state. each il pi n can be individually pro- grammed as a logic input or output by writing the appropri- ate instruction to the ldr (see tables 2 and 5). for minimum power dissipation, unconnected latch pins should be programmed as outputs. bits l 5 ?l 0 must be set by writing the specified instruction to the ldr with the l bits in the second byte set as follows. table 5. byte 2 functions of latch direction register note: x = don't care. interface latch states interface latches configured as outputs assume the state determined by the appropriate data bit in the 2-byte instruction written to the interface latch register (ilr) as shown in tables 2 and 6. latches configured as inputs sense the state applied by an exte rnal source, such as the off- hook detect output of a slic. all bits of the ilr, i.e., sensed inputs and the programmed state of outputs, can be read back in the second byte of a read of the ilr. it is recommended that during initialization, the state of il pins to be configured as outputs should be programmed first, followed immediately by the ldr. table 6. interface latch data bit order bit number time-slot assignment the t7570 can operate in either fixed time-slot or time-slot assignment mode for selecting the transmit and receive pcm time slots. following powerup, the device is automatically in nondelayed timing mode, in which the time slot always begins with the leading (rising) edge of frame-sync inputs fs x and fs r . time-slot assignment can only be used with delayed-data timing (see figure 5). fs x and fs r can have any phase relationship with each other in bclk period increments. alternatively, the internal time-slot assignment counters and comparators can be used to access any time slot in a frame by using the frame-sync inputs as marker pulses for the beginning of transmit and receive time slots of 8 bits each. a time slot is assigned by a 2-byte instruction as shown in tables 2 and 7. the last 6 bits of the second byte indicate the selected time slot from 0 to 63 using straight binary notation. a new assignment becomes active on the second frame following the end of the cs for the second control byte. the en bit allows the pcm inputs, d r 0/1, or outputs, d x 0/1, as appropriate, to be enabled or disabled. time-slot assignment mode requires that the fs x and fs r pulses must conform to the delayed-data timing format shown in figure 5. port selection two transmit serial pcm ports, d x 0 and d x 1, and two receive serial pcm ports, d r 0 and d r 1, are provided to enable two-way space switching to be implemented. port selections for transmit and receive are made within the appropriate time-slot assignment instruction using the ps bit in the second byte. port selection can only be used in delayed-data timing mode. table 7 shows the format of the second byte of both transmit and receive time-slot and po rt assignment instructions. byte 2 bit number 76543210 l 0 l 1 l 2 l 3 l 4 l 5 xx l n bit il direction 0 input 1 output bit number 76543210 d 0 d 1 d 2 d 3 d 4 d 5 xx not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 10 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 functional description (continued) programmable functions (continued) table 7. time-slot and port assignment instruction * t 5 is the msb of the time-slot assignment. bit number and name function 76543210 en ps t 5 * t 4 t 3 t 2 t 1 t 0 0 0 xxxxxxdisable d x 0 output (transmit instruction) disable d r 0 input (receive instruction) 0 1 xxxxxxdisable d x 1 output (transmit instruction) disable d r 1 input (receive instruction) 1 0 assign one binary-coded time slot from 0?63 enable d x 0 output (transmit instruction) enable d r 0 input (receive instruction) 1 1 assign one binary-coded time slot from 0?63 enable d x 1 output (transmit instruction) enable d r 1 input (receive instruction) transmit gain instruction byte 2 the transmit gain can be programmed in 0.1 db steps from ? 0.4 db to +19.0 db by writing to the transmit gain register as defined in tables 2 and 8. this corresponds to a range of 0 dbm0 levels at vf x i between 0.811 vrms and 0.087 vrms (equivalent to +0.4 dbm to ? 19.0 dbm into 600 ? ). to set transmit gain, determine the gain required of the codec in order to achieve the overall desired transmission level point (tlp) at the pcm interface (usually 0 dbm or ?2 dbm). in order for the internal hybrid -balance circuitry to be effec- tive, the portion of vf r o returned to the codec analog input must be between ?2.5 db to ?10.25 db of the vf r o output. for instance, if a slic presents a ?6 dbm signal to vf x i when vf r o produces 0 dbm, good hybrid balance can be achieved . if the returned signal requires amplification to satisfy this requirement, then an additional op amp in the transmit path would be required. the t7570 will accommodate the phase inversion. a spare op amp is provided in some legerity slics. once the codec gain is chosen , determine what signal level at vf x i would provide the desired tlp output at dx. for our example of +6 db gain (gx) providing a 0 dbm tlp and working backwards from dx, take the anti- log of minus 6 db divided by 20 and multiply by the 0.7746 reference level to obtain the signal level at vf x i in vrms. as follows: (1) antilog 10 (?gx / 20) * 0.7746 = vrms finally, convert the signal level to a decimal number (n) using the following formula: (2) 200 * log 10 (vrms / 0.08592) = n round n to the nearest integer and convert to binary. this is the code required by byte 2 of this instruction. some exam- ples are given in table 8. table 8. byte 2 of transmit gain instructions * 0 db path gain setting. ? programming values greater than thos e listed in this table are permitted. however, large signals may cause overload. receive gain inst ruction byte 2 the receive gain can be progra mmed in 0.1 db steps from ? 17.3 db to +2.1 db by writing to the receive gain register as defined in tables 2 and 9. this corresponds to a range of 0 dbm0 levels at vf r o between 0.987 vrms and 0.106 vrms (equivalent to +2.1 dbm to ? 17.3 dbm into 600 ? ). bit number 0 dbm0 test level (vrms) 7 6 5 4 3 2 1 0 at vf x i 0 0 0 0 0 0 0 0 no output 0 0 0 0 0 0 0 1 0.087 0 0 0 0 0 0 1 0 0.088 ?? 1 0 1 1 1 1 1 1* 0.7746 ?? 1 1 0 0 0 0 1 0 0.802 1 1 0 0 0 0 1 1 ? 0.811 not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 11 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter functional description (continued) programmable functions (continued) to set receive gain, first determ ine the gain required of the codec. for line card use, determine the codec?s allocation to set the overall transmission level point (tlp) at tip\ring accordingly (usually 0 dbm or ?4 dbm). once the codec gain is chosen, determine the signal level that would be delivered to vf r o when the reference tlp appears at d r . take the antilog of the gain in db (g r ) divided by 20 and multiply by the 0.7746 reference level to obtain the signal level at vf r o in vrms. as follows: (3) antilog 10 (g r / 20) * 0.7746 = vrms finally, convert the signal level output to a decimal number (n) using the following formula: (4) 200 * log 10 (vrms / 0.1045) = n round n to the nearest integer and convert to binary. this is the code required by byte 2 of this instruction. some exam- ples are given in table 9. table 9. byte 2 of r eceive gain instructions * 0 db path gain setting. ? programming values greater than those listed in th is table are permitted. however, large signals may cause overload. hybrid-balance filter the hybrid-balance filter on the t7570 is a programmable filter consisting of a second-order section, hybal1, followed by a first-order section, hybal2 , and a programmable attenu- ator. either of the filter sections can be bypassed if only one is required to achieve good cancellation. a selectable 180 inverting stage is included to compensate for interface cir- cuits that invert the transmit in put relative to the receive out- put signal. the second-order s ection is intended mainly to balance low-frequency signal s across a transformer slic, bit number 0 dbm0 test level (vrms) 7 6 5 4 3 2 1 0 at vf r i 0 0 0 0 0 0 0 0 no output (low z to gnd) 0 0 0 0 0 0 0 1 0.106 0 0 0 0 0 0 1 0 0.107 ?? 1 0 1 0 1 1 1 0* 0.7746 ?? 1 1 0 0 0 0 1 0 0.975 1 1 0 0 0 0 1 1 ? 0.987 and the first-order section is intended to balance midrange to higher audio-frequency signals. as a second-order section, h ybal1 has a pair of low-fre- quency zeros and a pair of complex conjugate poles. when configuring the hybal1, matching the phase of the hybrid at low- to midband frequencies is most critical. once the echo path is correctly balanced in phase, the magnitude of the cancellation signal can be co rrected by the programmable attenuator. the second-order mode of hybal1 is most suitable for bal- ancing interfaces with transf ormers having high inductance of 1.5 h or more. an alternative configuration for smaller transformers is available by co nverting hybal1 to a simple first-order section with a sing le real low-frequency pole and zero. in this mode, the pole/zero frequency can be programmed. many line interfaces can be adequately balanced by use of the hybal1 filter only, in which case the hybal2 filter should be deselected to bypass it. hybal2, the higher-frequency first-order section, is provided for balancing an electronic slic and is also helpful with a transformer slic in providi ng additional phase correction for mid- and high-band frequencies, typically 1 khz to 3.4 khz. such a correction is partic ularly useful if the test bal- ance impedance includes a capacitor of 100 nf or less, such as the loaded and nonloaded loop test networks in the united states. independent placement of the pole and zero location is provided. figure 3 shows a simplified diag ram of the local echo-path for a typical application with a transformer interface. the magnitude and phase of the local echo signal, measured at vf x i, are a function of the termination impedance z t , the line transformer, and the impedance of the two-wire loop, z l . if the impedance reflected b ack into the transformer pri- mary is expressed as z l ' , then the echo path transfer function from vf r o to vf x i is the following: (5) h(w) = z l ' /(z t + z l ' ) the signal level returned at vf x i must be between ?2.5 db to ?10.25 db over the voice band, relative to the output at vf r o, in order for the hybrid balance function to be effective. signals outside this range exceed the range of programmability of the hybrid path, and the software will provide unacceptable hybrid ba lance performance over the voice band. not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 12 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 functional description (continued) hybrid-balance filter (continued) figure 3. block diagram hybrid-balance filter network 5-2788 (f) 2.4 hybal1 first- or second- order filter (reg 2) set in reg 2 hybal2 first- order filter (reg 3) hi freq attenuator gain sel 2 to tx gain block from rx gain block inv 1 ? + sel 2.4 r vpxi vf x i vf r o z t z l zl tip ring programming the filter on initial powerup, the hybrid-balance filter is disabled. before the hybrid-balance filter can be programmed, it is necessary to design the transformer and termination imped- ance to meet system 2-wire in put return loss specifications, which are normally measured ag ainst a fixed test impedance (600 ? or 900 ? in most countries). only then can the echo path be modeled and the hybrid-balance filter programmed. hybrid balancing is also measured against a fixed test impedance, specified by each national telecommunication administration to provide adequate control of talker and lis- tener echo over the majority of their network connections. this test impedance is z l in figure 3. the echo signal and the degree of transhybrid loss obtained by the programmable filter must be measured from the pcm digital input, d r 0/1, to the pcm digital output, d x 0/1, either by digital test signal analysis or by conversion back to analog by a pcm codec/ filter. three registers must be programmed in the t7570 to fully configure the hybrid-balance filte r (refer to table 2 for byte 1 addressing): register 1: select/deselect h ybrid-balance f ilter; invert/ noninvert cancellation signal; select/deselect hybal2 filter section; set attenuator. register 2: select/deselect hybal1 filter; set hybal1 to biquad or first order; select pole and zero frequency. register 3: program pole frequency in hybal2 filter; pro- gram zero frequency in hybal2 filter. standard filter design techniques can be used to model the echo path (see equation 5) and design a matching hybrid- balance filter configuration. alternatively, the frequency response of the echo path can be measured and the hybrid- balance filter design ed to replicate it. t7570 hybrid-balance software is available from your legerity account representative to aid in selecting the best balance filter register settings. byte 2 of register 1 76 5 43210 sel inv sel2 gain (all 0 = max) not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 13 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter functional description (continued) hybrid-balance filter (continued) power supply while the pins of the t7570 devices are we ll protected against electrical misuse, it is recommended that the standard cmos practice of applying gnd to the device before any other connec tions are made should always be followed. in applications where the printed-circuit card can be plugged into a hot socket with power and clocks already present, an extra-long ground pin on the connector should be used. to minimize noise sources, all gr ound connections to each device sh ould meet at a comm on point as close as possible to the device gnd pin to prevent the interaction of ground return currents flowing through a common-bus impedance. a power-sup- ply decoupling capacitor of 0.1 f should be connected from this common point to v dd, as close to the device pins as possi- ble. the power supply should also be decoupled with a lo w, effective series resistan ce capacitor of at least 10 f, located near the card edge connector. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause pe rmanent damage to the device. these are absolute stress rat- ings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to elec- trostatic discharge (esd) during handling and mounting. lege rity employs a human-body model (hbm) and a charged-device model (cdm) for esd susceptibility testing and protection desi gn evaluation. esd voltage thresholds are dependent on the circuit parameters used to define the m odel. no industry-wide standard has been adopted for cdm. however, a standard hbm (resistance = 1500 ? , capacitance = 100 pf) is widely used and therefore can be used for comparison purposes. the hbm esd threshold presented here was obta ined using these circuit parameters. table 10. human-body model esd threshold parameter symbol min max unit storage temperature range t stg ?55 150 c power supply voltage v dd ?6.5 v voltage on any pin with respect to ground ? ?0.5 0.5 + v dd v maximum power dissipation (package limit) p diss ?600mw device voltage t7570 2000 v not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 14 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 electrical characteristics for all tests, t a = ?40 c to +85 c, v dd = 5 v 5%, and gnd = 0 v, unless otherwise noted. typical values are for t a = 25 c and nominal supply values. dc characteristics table 11. digital interface table 12. power dissipation parameter symbol test conditions t a ( c) min max unit input voltage low v il all digital inputs ? ? 0.7 v high v ih all digital inputs ? 2.0 ? v output voltage low v ol d x 0, d x 1, co, i l = 3.2 ma ? ? 0.4 v all other digital outputs, i l = ?1 ma ? ? 0.4 v high v oh d x 0, d x 1, co, i l = 3.2 ma ? 2.4 ? v all other digital outputs except ts x , i l = ?1 ma ?2.4?v all digital outputs, i l = ?100 a?v cc ? 0.5 ? v input current low i il any digital input, gnd < v in < v il ? ?1010 a high i ih any digital input except mr, v ih < v in < v cc ? ?1010 a mr only ? ?10 100 a output current in high-imped- ance state ?i oz d x 0, d x 1, co, il5?il0 when selected as inputs, gnd < v out < v cc ?40 to 0 ?30 30 a 0 to 85 ?10 10 a parameter symbol test conditions typ max unit powerdown current i dd 0 cclk, ci, co = 0.4 v, cs = 2.4 v, interface latches set as outputs with no load, all other inputs active, power amp enabled 0.3 0.9 ma powerup current i dd 1 cclk, ci, co = 0.4 v, cs = 2.4 v, no load on power amp, interface latches set as outputs with no load 14.0 20.0 ma powerdown current i dd 2 cclk, ci, co = 0.4 v, cs = 2.4 v, interface latches set as outputs with no load, all other inputs active, power amp enabled, no load on power amp 4.0 6.0 ma not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 15 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter transmission characteristics table 13. analog interface table 14. gain and dynamic range parameter symbol test conditions min typ max unit input resistance r vfxi 0.25 v < vf x i < 4.75 v 390 585 ? k ? input offset voltage at vf x ivos x ? 2.3?2.5v load resistance rl vfro ? 300 ? ? ? load capacitance cl vfro rl vfro 300 ? cl vfro from vf r o to gnd ? ? 200 pf output resistance ro vfro steady zero pcm code applied to d r 0 or d r 1?1.63.0 ? output offset voltage at vf r o vos r alternating zero pcm code applied to d r 0 or d r 1, maximum receive gain 2.3?2.5 v output offset voltage at vf r o, powerdown vos rpd control register byte 2, bit 7 = 0 2.3 ? 2.5 v output voltage swing v swr rl = 300 ? , maximum receive gain 4.01 ? ? v pp parameter symbol test conditions t a ( c) min typ max unit absolute levels g al maximum 0 dbm0 levels: vf x i (gain set to 11000011) ? ? 0.811 ? vrms vf r o (gain set to 11000011) ? ? 0.987 ? vrms minimum 0 dbm0 levels: vf x i (gain set to 00000001) ? ? 87.0 ? mvrms vf r o (gain set to 00000001) ? ? 106.0 ? mvrms transmit gain g xa transmit gain programmed for maximum 0 dbm0 test level, mea- sured deviation of digital code from ideal 0 dbm0 pcm code at d x 0/1, t a = 25 c ? ?0.15 ? 0.15 db absolute accuracy transmit gain variation with temperature g xat measured relative to g xa , v dd = 5 v, minimum gain < g x < maximum gain ?40 to 0 ?0.15 ? 0.15 db 0 to 85 ?0.1 ? 0.1 db transmit gain variation with programmed gain g xag measured transmit gain over the range from maximum to minimum, calculated the deviation from the programmed gain relative to g xa (i.e., g xaf = g actual ? g prog ? g xa ), t a = 25 c, v dd = 5 v ? ?0.1 ? 0.1 db not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 16 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 transmission characteristics (continued) table 14. gain and dynamic range (continued) parameter symbol test conditions t a ( c) min typ max unit transmit gain variation with frequency g xaf relative to 1020 hz, minimum gain < g x < maximum gain, d r 0 or d r 1 = 0 dbm0 code: f = 16.67 hz ? ? ?35 ?30 db f = 50 hz ? ? ?33 ?30 db f = 60 hz ? ? ?40 ?30 db f = 200 hz ? ?1.8 ?0.5 0 db f = 300 hz to 3000 hz ? ?0.125 0.04 0.125 db f = 3140 hz ? ?0.57 0.01 0.125 db f = 3380 hz ? ?0.885 ?0.6 0.012 db f = 3860 hz ? ? ?9.9 ?8.98 db f 4600 hz (measured response at alias frequency from 0 khz to 4 khz) ? ? ? ?32 db transmit gain variation with signal level g xal sinusoidal test method, reference level = 0 dbm0: vf x i = ?40 dbm0 to +3 dbm0 ? ?0.2 ? 0.2 db vf x i = ?50 dbm0 to ?40 dbm0 ? ?0.4 ? 0.4 db vf x i = ?55 dbm0 to ?50 dbm0 ? ?1.2 ? 1.2 db receive gain absolute accuracy g ra receive gain programmed for max- imum 0 dbm0 test level, applied 0 dbm0 pcm code to d r 0 or d r 1, measured vf r o, t a = 25 c, load = 10 k ? ? ?0.15 ? 0.15 db receive gain variation with temperature g rat measured relative to g ra , v dd = 5 v, minimum gain < g r < maximum gain ?40 to 0 ?0.15 ? 0.15 db 0 to 85 ?0.1 ? 0.1 db receive gain variation with programmed gain g rag measured receive gain over the range from maximum to minimum setting, calculated the deviation from the programmed gain relative to g ra , i.e., g rag = g actual ? g prog ? g ra , t a = 25 c, v dd = 5 v ? ?0.1 ? 0.1 db not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 17 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter transmission characteristics (continued) table 14. gain and dynamic range (continued) table 15. envelope delay distortion parameter receive gain variation with frequency symbol test conditions t a ( c) min typ max unit g raf relative to 1020 hz, d r 0 or d r 1 = 0 dbm0 code, minimum gain < g r < maximum gain: f 3000 hz ? ?0.125 0.04 0.125 db f = 3140 hz ? ?0.57 0.01 0.125 db f = 3380 hz ? ?0.885 ?0.58 +0.012 db f = 3860 hz ? ? ?10.7 ?8.98 db f 4600 hz ? ? ? ?28 db receive gain variation with signal level g ral sinusoidal test method, reference level = 0 dbm0: d r 0 = ?40 dbm0 to +3 dbm0 ? ?0.2 ? 0.2 db d r 0 = ?50 dbm0 to ?40 dbm0 ? ?0.4 ? 0.4 db d r 0 = ?55 dbm0 to ?50 dbm0 ? ?1.2 ? 1.2 db parameter symbol test conditions min max unit tx delay, absolute d xa f = 1600 hz ? 315 s tx delay, relative to 1600 hz d xr f = 500 hz?600 hz ? 220 s f = 600 hz?800 hz ? 145 s f = 800 hz?1000 hz ? 75 s f = 1000 hz?1600 hz ? 40 s f = 1600 hz?2600 hz ? 75 s f = 2600 hz?2800 hz ? 105 s f = 2800 hz?3000 hz ? 155 s rx delay, absolute d ra f = 1600 hz ? 200 s rx delay, relative to 1600 hz d rr f = 500 hz?1000 hz ?40 ? s f = 1000 hz?1600 hz ?30 ? s f = 1600 hz?2600 hz ? 90 s f = 2600 hz?2800 hz ? 125 s f = 2800 hz?3000 hz ? 175 s not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 18 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 transmission characteristics (continued) table 16. noise * ppsr x is measured with a ?50 dbm0 activation signal applied to vf x i. parameter symbol test conditions min typ max unit transmit noise, c message weighted, -law selected n xc all 1s in gain register ? ? 15 dbrnc0 transmit noise, p message weighted, a-law selected n xp all 1s in gain register ? ? ?67 dbm0p receive noise, c message weighted, -law selected n rc pcm code is alternating positive and negative zeros ? ? 13 dbrnc0 receive noise, p message weighted, a-law selected n rp pcm code equals positive one lsb ? ? ?79 dbm0p noise, single frequency n rs f = 0 khz?100 khz, analog to analog measurement (d x 0 is externally con- nected to d r 0), vf x i = 0 vrms ? ? ?53 dbm0 power supply rejection, transmit ppsr x v dd = 5.0 vdc + 100 mvrms: f = 0 khz?4 khz* f = 4 khz?50 khz 36 30 ? ? ? ? dbc dbc power supply rejec tion, receive ppsr r pcm code equals positive one lsb, v dd = 5.0 + 100 mvrms, measured vf r o: f = 0 hz?4000 hz 36 ? ? dbc f = 4 khz?25 khz 40 ? ? db f = 25 khz?50 khz 36 ? ? db spurious out-of-ban d signals at the channel output sos 0 dbm0, 300 hz?3400 hz input pcm code applied at d r 0 (or d r 1): 4600 hz?7600 hz ? ? ?30 db 7600 hz?8400 hz ? ? ?40 db 8400 hz?50,000 hz ? ? ?30 db not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 19 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter transmission characteristics (continued) table 17. distortion table 18. crosstalk * ct r?x and ppsr x are measured with a ?50 dbm0 activation signal applied to vf x i. parameter symbol test conditions min max unit signal to total distortion transmit or receive half-channel, -law selected std x std r sinusoidal test method level: 3.0 dbm0 33 ? dbc 0 dbm0 to ?30 dbm0 36 ? dbc ?40 dbm0 30 ? dbc ?45 dbm0 25 ? dbc single frequency distortion, trans- mit sfd x ? ? ?46 db single frequency distortion, receive sfd r ? ? ?46 db intermodulation distortion imd transmit or receive two frequencies in the range (300 hz?3400 hz) ? ?41 db parameter symbol test conditions typ max unit transmit to receive crosstalk, 0 dbm0 transmit level ct x?r f = 300 hz?3400 hz d r = steady pcm code ?90 ?75 db receive to transmit crosstalk, 0 dbm0 receive level ct r?x f = 300 hz?3400 hz* ?90 ?70 db not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 20 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 timing characteristics a signal is valid if it is above v ih or below v il and invalid if it is between v il and v ih . for the purposes of this specification, the following conditions apply: all input signals are defined as v il = 0.4 v, v ih = 2.7 v, t r < 10 ns, t f < 10 ns. t r is measured from v il to v ih . t f is measured from v ih to v il . delay times are measured from the input signal valid to the output signal valid. setup times are measured from the data input valid to the clock input invalid. hold times are measured from the clock signal valid to the data input invalid. pulse widths are measured from v il to v il or from v ih to v ih . table 19. master clock timing (see figures 4 and 5.) symbol parameter test conditions min typ max unit fmclk frequency of mclk?selection frequency is programmable (see table 3.) ?? ? ? ? 1536 1544 2048 4096 ? ? ? ? khz khz khz khz tmchmcl time of mclk high measured from v ih to v ih 80 ? ? ns tmclmch time of mclk low measured from v il to v il 80 ? ? ns tmch1mch2 rise time of mclk measured from v il to v ih ??30 ns tmcl2mcl1 fall time of mclk measured from v ih to v il ??30 ns tbclmch hold time, bclk low to mclk high ?50??ns tfslfsh period of fs x or fs r low measured from v il to v il 1??mclk period not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 21 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter timing characteristics (continued) table 20. pcm interface timing (see figures 4 and 5.) symbol parameter test conditions t a ( c) min max unit fbclk frequency of bclk (can vary from 64 khz to 4096 khz in 8 khz increments) ? ? 64 4096 khz tbchbcl time of bclk high measured from v ih to v ih ?80?ns tbclbch time of bclk low measured from v il to v il ?80?ns tbch1bch2 rise time of bclk measured from v il to v ih ? ? 30 ns tbcl2bcl1 fall time of bclk measured from v ih to v il ? ? 30 ns tbclfxl tbclfrl hold time, bclk low fs x/r to high or low ? ? 30 ? ns tfxhbcl tfrhbcl setup time fs x/r , high to bclk low ? ? 30 ? ns tbchdxv delay time, bclk high to data valid load = 100 pf plus two lsttl loads ? ? 90 ns tbcldxz delay time, bclk low to d x 0/1 disabled if fs x low, fs x low to d x 0/1 disabled if eighth bclk low, or bclk high to d x 0/1 disabled if fs x high ? ?40 to 0 10 80 ns 0 to 85 15 80 ns tbchtxl delay time, bclk high to ts x low if fs x high, or fs x high to ts x low if bclk high load = 100 pf plus two lsttl loads ? ? 60 ns tbcltxh high-impedance time, bclk low to ts x high if fs x low, or fs x bclk high to ts x high if fs x high ? ? 15 60 ns tfxhdxv delay time, fs x/r high to data valid load = 100 pf plus two lsttl loads, applies if fs x/r rises later than bclk rising edge in nonde- layed-data mode only ? ? 80 ns tdrvbcl setup time, d r 0/1 valid to bclk low ? ? 30 ? ns tbcldrx hold time, bclk low to d r 0/1 invalid ? ?40 to 0 15 ? ns 0 to 85 20 ? ns tbclmch bclk low to mclk high at the end of the first data bit period ? ? 50 ? ns not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 22 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 timing characteristics (continued) note: bit 1 = sign bit. figure 4. nondelayed-data timing mode note: bit 1 = sign bit. figure 5. delayed-data timing mode 5-2789 (c) 5-2790 (c) not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 23 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter timing characteristics (continued) table 21. serial control port timing (see figure 6.) table 22. interface latch timing (see figure 6.) table 23. master reset pin symbol parameter test conditions min max unit fcclk frequency of cclk ? ? 2048 khz tcchccl time of cclk high measured from v ih to v ih 160 ? ns tcclcch time of cclk low measured from v il to v il 160 ? ns tcch1cch2 rise time of cclk measured from v il to v ih ?50ns tccl2ccl1 fall time of cclk measured from v ih to v il ?50ns tcclcsl hold time, cclk low to cs low measured from first cclk low transition 10 ? ns tcclcsh hold time, cclk low to cs high measured from eighth cclk low transition 100 ? ns tcslcch setup time, cs transition to cclk low ?60?ns tcshcch setup time, cs transition to cclk high ?50?ns tcivccl setup time, ci data in to cclk low ?50?ns tcclcix hold time, cclk low to ci invalid ?50?ns tcchcov delay time, cclk high to co data out valid load = 100 pf plus 2 lsttl loads ? 80 ns tcslcov delay time, cs low to co valid applies only if separate cs used for byte 2 ?80ns tcshcoz delay time, cs high to co high impedance applies when cs high occurs before ninth cclk high 15 80 ns symbol parameter test conditions min max unit tilxccl setup time, il to eighth cclk of byte 1 interface latch inputs only 100 ? ns tcclilx hold time, il valid from eighth cclk low (byte 1) ?50?ns tcclilv delay time cclk 8 of byte 2 to il interface latch outputs only c l = 50 pf ? 200 ns symbol parameter min max unit tmrhrml duration of master reset high 1 ? s not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 24 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 timing characteristics (continued) figure 6. serial control port timing 5-2791 (c) not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 25 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter applications figure 7 illustrates a t7570 codec interfaced to a l75 54 slic. interface components were chosen for a basic 600 ? resistive only termination and balance networ k. overall receive path gain is 0 db (pcm to t/r). overall transmit pa th gain is ?2 db (t/ r to pcm). codec receive gain is 0 db. the signal level returned to vf x i is ?3.658 dbm. this satisfies the transmission level point requirement for hybrid cancellation. that is, the signal at vf x i relative to the output at vf r o must be within ?2.5 db to ?10.25 db. transmit gain of the codec is set at +1.658 db in order to achieve a transmission level point at dx of ?2 dbm. transmit and receive paths are capacitively coupled to accommodate differ ent slic and codec bias levels. the codec?s inputs are self-biased so that no additional external resistors are n ecessary with ac coupling. capaci tor values are sized appropriate ly to pass low-frequency requirements of releva nt gain versus frequency templates. resi stive values were ascertained from slic documentation. an optional 20 k ? resistor from rcvn to ground and a 30 pf capacitor across rgp can be added for stability. gain and hybrid-balance register values ar e shown in hex. gain values were obtained from tables 8 and 9. hybrid- balance values were obtained by removing the code c and inserting a network analyzer to meas ure the phase and gain returned by the loop to vf x i when a signal is injected at vf r o. gain and phase are then measured at 14 frequencies. the results obtained from this exercise are plu gged into the hybrid-balance software that provides the register settings as shown. figure 7. 600 ? resistive slic interface register settings register register numb er value description rx gain 04 ae 0 db tx gain 05 ae 1.658 db hybrid 1 06 a4 ? hybrid 2 07 51 ? hybrid 3 08 88 ? 5-4716 (f).a see register settings below vf r o rcvn vf x i vi tr 0.47 f 0.1 f 48.7 k ? rgp t7570 t7554 cc1 20 k ? crcv1 rrcv codec slic rt1 86.6 k ? rcvp 2.4 v 35 ? rpt pr 35 ? rpt pt 600 ? tz not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 26 t7570 programmable pcm codec data sheet with hybrid-balance filter august 2004 outline diagrams 28-pin plcc dimensions are shown in inches. 5-2608 (f)r.4 1.27 typ 0.53 0.10 seating plane 0.51 min typ 4.57 max 12 18 11 5 4126 25 19 12.57 max pin #1 identifier zone 11.58 max 11.58 12.57 max max not recommended for new designs no t recommended for new designs d i sc o n t i n u e d d e v i c e n o t r e c o m m e n d e d f o r n e w d e s i g n s not recommended for new designs not recommended for new designs 27 data sheet t7570 programmable pcm codec august 2004 with hybrid-balance filter ordering information device code package temperature comcode t - 7570 - - - ml2 28-pin plcc ?40 c to +85 c 107055782 t - 7570 - - - ml2 -tr 28-pin plcc, tape and reel ?40 c to +85 c 107056525 legerity, inc. reserves the right to make changes to the produc t(s) or information contained herein without notice. no liabilit y is assumed as a result of their use or application. copyright ? 2002 legerity, inc. all rights reserved |
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